A simple procedure to design Glitch-less switched-current cells - S, F.; oval-Ibarra.; Santana, J.; A, J.; Suárez-Lizárraga, G. (Revista Mexicana de Física, 2002)
The description of non-idealities in Cascode Switched-Current (SI) cell as well as its application in analog signal processing is described. A test chip (CMOS, 1.5μ m, N-well, 0-5 V) was designed to verify that the proposed method works successfully in the magnitude glitch reduction problem.