A simple procedure to design Glitch-less switched-current cells

F. S, oval-Ibarra. , J. Santana, J. A, G. Suárez-Lizárraga

Abstract


The description of non-idealities in Cascode Switched-Current (SI) cell as well as its application in analog signal processing is described. A test chip (CMOS, 1.5$\mu $m, N-well, 0-5 V) was designed to verify that the proposed method works successfully in the magnitude glitch reduction problem.

Keywords


Integrated circuits

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Revista Mexicana de Física

ISSN: 2683-2224 (on line), 0035-001X (print)

Bimonthly publication of Sociedad Mexicana de Física, A.C.
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