Impact of planarized gate electrode in bottom-gate thin-film transistors

M.A. Domínguez, P. Rosales, A. Torres, F. Flores, J.A. Luna, S. Alcantara, M. Moreno


In this work, the fabrication of bottom-gate TFTs with unplanarized and planarized gate electrode are reported, as well simulations of the impact of the gate planarization in the TFTs are presented. Previously in literature, a reduction of the contact resistance has been attributed to this planarized structure. In order to provide a physical explanation of this improvement, the electrical performance of ambipolar a-SiGe:H TFTs with planarized gate electrode by Spin-On Glass is compared with unplanarized ambipolar a-SiGe:H TFTs. Then, the properties in the main device interfaces are analyzed by physically-based simulations. The planarized TFTs have better characteristics such as field-effect mobility, on-current, threshold voltage and on/off-current ratio which are consequence of the improved contact resistance.


Thin-film transistor; hydrogenated amorphous silicon-germanium; simulation; planarization

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REVISTA MEXICANA DE FÍSICA, year 67, issue 1, January-February 2021. Bimonthly Journal published by Sociedad Mexicana de Física, A. C. Departamento de Física, 2º Piso, Facultad de Ciencias, Universidad Nacional Autónoma de México, Ciudad Universitaria, Alcaldía Coyacán, C.P. 04510 , Ciudad de México. Apartado Postal 70-348. Tel. (+52)55-5622-4946,, e-mail: Chief Editor: José Alejandro Ayala Mercado. INDAUTOR Certificate of Reserve: 04-2019-080216404400-203, ISSN: 2683-2224 (on line), 0035-001X (print), both granted by Instituto Nacional del Derecho de Autor. Responsible for the last update of this issue, Technical Staff of Sociedad Mexicana de Física, A. C., Fís. Efraín Garrido Román, 2º. Piso, Facultad de Ciencias, Universidad Nacional Autónoma de México, Ciudad Universitaria, Alcaldía Coyacán, C.P. 04510 , Ciudad de México. Date of last modification, January 4, 2021.

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