A noise tolerant technique for submicron dynamic digital circuits

Abstract

Signal integrity issues are a main concern in high performance circuits due to technological advancement. The smaller size of the CMOS transistors together with the increasing use of dynamic logic has brought signal integrity issues to the forefront. Hence it is necessary to develop noise-tolerant circuit techniques that will tolerate noise effects with slight performance penalties. In this paper a new noise tolerant dynamic digital circuit technique is proposed and demonstrated. Simulation results for CMOS AND gate show that the proposed technique has an improvement in the ANTE metric of 3.4x over conventional dynamic logic. A one-bit carry look-ahead adder implemented with the proposed technique has been designed and fabricated using an AMS 0.35$\mu $m CMOS N-well process. The experimental results show the noise immunity improvements of ANTE by 2.1x over the conventional dynamic circuit.