Design and simulation of hybrid SET-CMOS inverter using macro-model technique

Authors

  • Moulay Said EL KAZDIR Cadi Ayyad University, Faculty of Sciences Semlalia
  • M. Rzaizi Cadi Ayyad University, Faculty of Sciences Semlalia
  • K. El Assali Cadi Ayyad University, Faculty of Sciences Semlalia
  • D. Abouelaoualim Cadi Ayyad University, Faculty of Sciences Semlalia

DOI:

https://doi.org/10.31349/RevMexFis.68.061401

Keywords:

Single electron transistor (SET); macro-modeling; simscape; logic Inverter; hybrid SET-CMOS logic

Abstract

The single-electron transistor (SET) is one of the frontier device that can offer high operating speed at an ultra-low power consumption. SET macro-modeling, can be used for a SET-CMOS circuit simulation. In this work, we develop a new macro model of SET- CMOS hybrid whose is very useful effect in VLSI circuits design. All simulations are performed using environment SIMSCAPE of MATLAB SIMULINK. This architecture were realized by implementing the NMOS of conventional inverter with a SET macro-model. The simulation results show that the hybrid structure offers better performance. Indeed, the designed circuits are able to work at room temperature.

References

K. L. Wang, J. Nanosci Nanotechnol 2 (2002) 235.

E. Brandon Strong, S. A. Schultz, A. W. Martinez and N. W. Martinez, Sci. Rep. 9 (2019) 1.

P. Zhang, S. Xue, and J. Wang, Matr. Des. 192 (2020) 108726.

Q. Hongwei, Micromachines 7 (2016) 14.

S. Veeraraghavan and J. G. Fossum, IEEE Trans. Electron Devices, 36 (1989) 522.

U. Karki and F. Zheng Peng, IEEE Trans. Power Electron, 33 (2018) 10764.

S. M. Sharrousha and Y. S. Abdalla, Math Comput Model Dyn Syst., 27 (2021) 50.

C. Rai, A. Khursheed and F. Z. Haque, Austin J. Nanomed Nanotechnol, 7 (2019) 1055.

L. Jia Yen, A. Radzi Mat Isa, and K. Ahmad Dasuki, J. Fundam. Sci. 1 (2005).

M. K. Bera, East, Eur. J. Phys 4 (2020) 21-27.

J. Jasmine and M.E. Shajini Sheeba, Eur. J. Mol. Clin. Med. 7 (2020) 2425.

S. Dhar, M. Pattanaik, and P. Rajaram, VLSI Design, 1 (2011) 178516.

A. Mostefai, Carpathian J. Electr. Comp. Eng., 12/1 (2019) 23.

M. Aarthy, S. Sridev, JACSA, 11 (2020) 117.

B. Anishfathima, M. Mahaboob, EAI Endorsed Trans. Energy Web. 8 (2020).

A. Boubaker, M. Troudi, Na. Sghaier, A. Souifi, N. Baboux and A. Kalboussi. Microelectronics Journal 40 (2009) 543.

V. S. Zharinov, T. Picot, a J. E. Scheerder, E. Janssens and J. V. de Vondel, Nanoscale 12 (2020) 1164.

Y. amanakay, T. Moriez, M. Nagata and A. Iwata, Nanotechnology 11 (2000) 154.

A. Touati, S. Chatbouri, and K. Adel, ISRN nanotechnol, 587436 (2013).

M. Ashter Mehdy, M. Graziano, and G. Piccinini, IJECE, 8 (2018) 900.

A. Venkataratnam, A. K. Goel, Microelectronics Journal 39 (2008) 1461-1468.

R. Parekh, A. Beaumont, J. Beauvais, and D. Drouin, IEEE T ELECTRON DEV, 59 (2012) 918.

A. Jana, N. Basanta Sigh, J. K. Sing, S. Kumar Sarkar, Microelectron. Reliab, 53 (2013) 592.

F. Ali Hadi, S. Musa, Q. Kareem Omran and E. Abdulrazak Hussein, J. Phys. Conf. Ser. 1530 (2020)

M. H. Aziz and S. D. Al-Shamaa, AMS EEE 3 (2019) 144.

S. Mahapatra, V. Vaish, C. Wasshuber, K. Banerjee, and A. Ionescu, IEEE T ELECTRON DEV, 51 (2004) 1772.

M. Karimian, M. Dousti, M. Pouyan, R. Faez, IEEE Toronto International Conference Science and Technology for Humanity (TIC-STH), Toronto, (Canada 26-27 Sept. 2009).

A. Priya, N. Anand Srivastava, and R. Awadh Mishra, J. Nanotechnol, 1 (2019) 4935073.

K. Kishor Jha, A. Jain, M. Pattanaik, Anurag Srivastava, IEEE, (2010).

Y. S. Yu, S. W. Hwang, and D. Ahn, IEEE transaction on electron devices, 46 (1999) 1667.

Downloads

Published

2022-11-01

How to Cite

[1]
M. S. EL KAZDIR, M. Rzaizi, K. El Assali, and D. Abouelaoualim, “Design and simulation of hybrid SET-CMOS inverter using macro-model technique”, Rev. Mex. Fís., vol. 68, no. 6 Nov-Dec, pp. 061401 1–, Nov. 2022.

Issue

Section

14 Other areas in Physics