Diseño de amplificadores CMOS usando gm/ID y su uso como un sistema de primer orden
DOI:
https://doi.org/10.31349/RevMexFis.70.060901Keywords:
Electronic circuits for signal processing, CMOS amplifier, Integrated circuits, MOSFET, gm/ID methodologyAbstract
This paper presents the analysis and design of CMOS differential amplifiers using the first-order approach and sizing the transistors with the gm/ID methodology. The design of four amplifiers using parameters of a 130nm CMOS technology is shown, and through spice simulation basic concepts of performance and compliance specifications are verified. The comparison of the performance of the designed amplifiers, in the synthesis of an active low-pass filter, is made to show that the fundamental performance parameters of each amplifier, affects the expected performance of the circuit under design, showing that the CMOS amplifier is not general purpose but that the application takes advantage of the characteristics of the amplifier or, alternatively, the amplifier is designed to meet the requirements of the application. Finally, while each architecture is sized using the same general performance specifications, it is also true that each has a specific and unique overall performance. These differences can be obtained and understood with spice simulation, since the resources of the simulation tool are used properly. All results obtained are at room temperature.
En este trabajo se presenta el análisis y diseño de amplificadores diferenciales CMOS usando la aproximación de primer orden y dimensionando los transistores con la metodología gm/ID. Se muestra el diseño de cuatro amplificadores usando parámetros de una tecnología CMOS 130 nm, y mediante simulación spice se verifican conceptos básicos de desempeño y el cumplimiento de especificaciones. La comparación del desempeño de los amplificadores diseñados, en la síntesis de un filtro activo pasa-bajas, se hace para mostrar que los parámetros fundamentales de desempeño de cada amplificador, afecta el desempeño esperado del circuito bajo diseño, mostrando que el amplificador CMOS no es de propósito general sino que la aplicación aprovecha las características del amplificador o, alternativamente, el amplificador se diseña para satisfacer los requerimientos de la aplicación. Finalmente, si bien cada arquitectura se dimensiona usando las mismas especificaciones generales de desempeño, también es verdad que cada una presenta un desempeño global específico y único. Estas diferencias pueden obtenerse y entenderse con simulación spice, toda vez que se usan adecuadamente los recursos de la herramienta de simulación. Todos los resultados obtenidos son a temperatura ambiente.
References
J.-H. Tsai, S.-W. Huang, and J.-P. Chou, A 5.5 GHz lowpower PLL using 0.18-μm CMOS technology, In 2014 IEEE Radio and Wireless Symposium (RWS) (2014) pp. 205–207, https://doi.org/10.1109/RWS.2014.6830071.
G.-C. Hsieh and J. Hung, Phase-locked loop techniques. A survey, IEEE Transactions on Industrial Electronics 43 (1996) 609, https://doi.org/10.1109/41.544547
O. Kegege, et al., Mission optimization and tradeoffs of using SiGe based electronics for a cryogenic environment rover mission, In 2010 IEEE Aerospace Conference (2010) pp. 1–6, https://doi.org/10.1109/AERO.2010.5446757.
B. Razavi, Design of analog CMOS integrated circuits (McGraw-Hill, 2005), pp. 9–369.
R. J. Baker, CMOS: circuit design, layout, and simulation (John Wiley & Sons, 2019), pp. 161–930.
F. Cortes and S. Bampi, Miller OTA Design using a Design Methodology Based on the gm/Id and Early-Voltage Characteristics:
Design Considerations and Experimental Results, Proceedings of XII Workshop Iberchip (2006) 501
R. J. Van de Plassche, CMOS integrated analog-to-digital and digital-to-analog converters, vol. 742 (Springer Science & Business Media, 2013), pp. 1–104.
R. del Rio and M. Jose, CMOS sigma-delta converters: Practical design guide (John Wiley & Sons, 2013), pp. 1–76.
M. Sandoval-Ibarra, Cuesta-Claros, Design of 2nd order low-pass active filters by preserving the physical meaning of design variables, Rev. mex. fís. E [online] 57 (2011) 1, http://www.scielo.org.mx/scielo.php?script=sci_arttext&pid=S1870 35422011000100001&lng=es&nrm=iso
L. Kawecki, A new type of analog cosine converter, Rev.mex. fís. E [online] 52 (2006) 387, http://www.scielo.
org.mx/scielo.php?script=sci_arttext&pid=S0035-001X2006000400015&lng=es&nrm=iso
P. S. Sushma, et al., Design of high gain bulk-driven millerOTA using 180nm CMOS technology, In 2016 IEEE InternationalConference on Recent Trends in Electronics, InformationCommunication Technology (RTEICT) (2016) pp. 1774–1777, https://doi.org/10.1109/RTEICT.2016.7808139.
S. I. Singh, Design of low-voltage CMOS two-stage operational transconductance amplifier, In 2017 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT) (2017) pp. 248–252, https://doi.org/10.1109/ICEECCOT.2017.8284677.
B. Gupta and U. Bansal, Design Of Low Power Floating Gate Miller OTA, In 2018 3rd IEEE International Conference on Recent Trends in Electronics, Information Communication Technology (RTEICT) (2018) pp. 195–199, https://doi.org/10.1109/RTEICT42901.2018.9012378.
A. D. Grasso, et al., High-Performance Three-Stage Single-Miller CMOS OTA With No Upper Limit of CL, IEEE Transactions on Circuits and Systems II: Express Briefs 65(2018) 1529, https://doi.org/10.1109/TCSII.2017.2756923
M. A. Mohammed and G. W. Roberts, A Scalable Many-Stage CMOS OTA for Closed-Loop Applications, In 2021 IEEE International Symposium on Circuits and Systems (ISCAS) (2021) pp. 1–5, https://doi.org/10.1109/ISCAS51556.2021.9401697.
R. S. Assaad and J. Silva-Martinez, The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier, IEEE Journal of Solid-State Circuits 44 (2009) 2535, https://doi.org/10.1109/JSSC.2009.2024819
Y. Li, et al., Transconductance enhancement method for operational transconductance amplifiers, Electronics letters 46 (2010) 1321, https://doi.org/10.1049/el.2010.1575
M. Ahmed, et al., An improved recycling folded cascode amplifier with gain boosting and phase margin enhancement, In 2015 IEEE International Symposium on Circuits and Systems (ISCAS) (2015) pp. 2473–2476, https://doi.org/10.1109/ISCAS.2015.7169186.
L. Kouhalvandi, et al., An improved 2 stage opamp with railto-rai! gain-boosted folded cascode input stage and monticelli rail-to-rail class AB output stage, In 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS) (2017) pp. 542–545, https://doi.org/10.1109/ICECS.2017.8292126.
M. P. Garde, et al., Super Class-AB Recycling Folded Cascode OTA, IEEE Journal of Solid-State Circuits 53 (2018) 2614, https://doi.org/10.1109/JSSC.2018.2844371
P. E. Allen and D. R. Holberg, CMOS analog circuit design (Elsevier, 2011), pp. 36–432.
B. Thandri and J. Silva-Martinez, A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors, IEEE Journal of Solid-State Circuits 38 (2003) 237, https://doi.org/10.1109/JSSC.2002.807410
R. Kumar, R. Nagulapalli, and S. K. Vishvakarma, A Novel Gain Enhanced Folded Cascode OPAMP in 28nm CMOS Technology, In 2022 International Conference on Electrical, Computer and Energy Technologies (ICECET) (2022)pp. 1–4, https://doi.org/10.1109/ICECET55527.2022.9872766.
D. Liu, et al., An Improved Recycling Folded-Cascode Amplifier with Nested Current Mirror for Front-end Readout ASIC, In 2022 IEEE 2nd International Conference on Electronic Technology, Communication and Information (ICETCI) (2022) pp. 281–284, https://doi.org/10.1109/ICETCI55101.2022.9832277.
A. V. Kayyil, et al., A Two-Stage CMOS OTA with Load-Pole Cancellation, In 2019 IEEE International Symposium on Circuits and Systems (ISCAS) (2019) pp. 1–5, https://doi.org/10.1109/ISCAS.2019.8702347.
P. Jespers, The gm/ID Methodology, a sizing tool for lowvoltage analog CMOS Circuits: The semi-empirical and compact model approaches (Springer Science & Business Media, 2009), pp. 1–48.
F. Silveira, D. Flandre, and P. Jespers, A g/sub m//I/sub D/ based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA, IEEE Journal of Solid-State Circuits 31 (1996) 1314, https://doi.org/10.1109/4.535416
F. P. Cortes, E. Fabris, and S. Bampi, A band-pass Gm-C Filter design based on gm/ID methodology and characterization, In Proceedings of the 19th annual symposium on Integrated circuits and systems design (2006) pp. 232–237, https: //doi.org/10.1145/1150343.1150401.
M. C. Schneider and C. Galup-Montoro, CMOS analog design using all-region MOSFET modeling (Cambridge University Press, 2010), pp. 1–175.
C. T. Chan, D. A. Johns, and K. W. Martin, Analog Integrated Circuit Design (2011).
L. Kouhalvandi, et al., An improved 2 stage opamp with railto- rai! gain-boosted folded cascode input stage and monticelli rail-to-rail class AB output stage, In 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS) (2017) pp. 542–545, https://doi.org/10.1109/ICECS.2017.8292126.
B. Lipka, et al., Design of a complementary folded-cascode operational amplifier, In 2009 IEEE International SOC Conference (SOCC) (2009) pp. 111–114, https://doi.org/10.1109/SOCCON.2009.5398081.
K. Kim and J. Silva-Martinez, Low-power 3rd-order continuous-time low-pass sigma-delta analog-to-digital converter for wideband applications, In 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) (2012) pp. 814–817, https://doi.org/10.1109/MWSCAS.2012.6292145.
B. Kamath, R. Meyer, and P. Gray, Relationship between frequency response and settling time of operational amplifiers, IEEE Journal of Solid-State Circuits 9 (1974) 347, https://doi.org/10.1109/JSSC.1974.1050527
R. L. Geiger and E. Sánchez-Sinencio, Active filter design using operational transconductance amplifiers: A tutorial, IEEE Circuits and Devices Magazine 1 (1985) 20, https://doi.org/10.1109/MCD.1985.6311946
S. D. Yu, Small-Signal Analysis of a Differential Two-Stage Folded-Cascode CMOS Op Amp, JSTS: Journal of Semiconductor Technology and Science 14 (2014) 768, https: //doi.org/10.5573/JSTS.2014.14.6.768
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