A simple procedure to design Glitch-less switched-current cells

Authors

  • F. S
  • oval-Ibarra.
  • J. Santana
  • J. A
  • G. Suárez-Lizárraga

Keywords:

Integrated circuits

Abstract

The description of non-idealities in Cascode Switched-Current (SI) cell as well as its application in analog signal processing is described. A test chip (CMOS, 1.5$\mu $m, N-well, 0-5 V) was designed to verify that the proposed method works successfully in the magnitude glitch reduction problem.

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Published

2002-01-01

How to Cite

[1]
F. S, oval-Ibarra., J. Santana, J. A, and G. Suárez-Lizárraga, “A simple procedure to design Glitch-less switched-current cells”, Rev. Mex. Fís., vol. 48, no. 3, pp. 182–0, Jan. 2002.

Issue

Vol. 48 No. 3 (2002): Revista Mexicana de Física.

Section

Articles

License

Authors retain copyright and grant the Revista Mexicana de Física right of first publication with the work simultaneously licensed under a CC BY-NC-ND 4.0 that allows others to share the work with an acknowledgement of the work's authorship and initial publication in this journal.